The present invention relates to a method of manufacturing folded capacitors for increasing the cell capacitance in a dynamic random access memory (DRAM) and folded capacitors fabricated thereby.
A dram cell for storing 1-bit datum has a MOS Transistor and a capacitor. The number of cells integrated per unit area becomes increased as the DRAM density increases. As a result, the available area for capacitor formation in a DRAM cell becomes reduced, which leads to a difficulty in obtaining a sufficient cell capacitance for the proper operation of DRAM.
These types of DRAM capacitors are existing : a planar capacitor, a stacked capacitor and a trench capacitor.
The planar capacitor is not applicable to the 4M DRAM or beyond, because it is not able to form 20-30fF capacitance per cell when the cell size is below 20 .mu.m.sup.2.
The stacked capacitor is formed by stacking conduction layer on the surface topography, which results in an effective cell capacitor area. This simple stacked capacitor has a limitation ot extend its usage to 64M DRAM or beyond as long as the dielectric thickness of capacitor is scaled down to below 50.ANG.. However, it is difficult to have ultra thin dielectric below 50.ANG. with good electric characteristics.
The trench capacitor is made by forming a trench to increase an effective capacitance area. However, the fabrication process of trench formation is so complicated that a DRAM with trench capacitor has a problem in the aspect of mass production.
In order to produce reliable ultra-high density DRAM's, efforts have been made to obtain sufficient cell capacitance on a limited capacitor area with a simple fabrication process.